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| a FEATURES Dual Measurement Channels Precision Four-Quadrant-Per-Pin V/I Source Programmable Current Force Ranges 204.8 A and 2.048 mA Five Current Measurement Ranges 204.8 nA to 2.048 mA Output Voltage Range: -4 V to +9 V Power Supplies: +15 V, +5 V, and -10 V 44-Lead Plastic J-Leaded Chip Carrier Package APPLICATIONS Can Be Used with the AD53032 DCL to Extend Current Force Range to 35 mA GENERAL DESCRIPTION PPMU Circuit AD53508 The device provides a remote force/sense capability to ensure accuracy at the tester pin. A guard output is available to drive the shield of a force/sense pair. Two input references per channel permit controlled switching to different voltage or current levels. The forced voltage or current levels can be switched back to the measurement system to read back the analog levels for system calibration. The circuit is powered by +15 V, +5 V and -10 V supplies and dissipates 230 mW nominally. Recommended Use of the PPMU with AD53032 DCL The AD53508 is a custom dual-channel parametric measurement circuit for use in semiconductor automatic test equipment. It contains programmable modes to force a pin voltage and measure its current or to integrate and hold a current value. Alternatively, a current can be forced and the compliance voltage measured. The PPMU can be used with the AD53032 DCL to extend the Current Force Range beyond 2 mA VCOM can be set to the maximum spec allowance of 8 V, which would allow the maximum Current Force of IOL of 35 mA. The combination of the PPMU and the DCL would have a few benefits including: 1. Accurately measuring low currents. 2. Can take parallel measurements by using one PMU per pin. FUNCTIONAL BLOCK DIAGRAM S8 S9 EXT RC MAIN S10 VF IF DSR +2.5V S2 OUTPUT S1 MEAS OUT CON 1.25R R GUARD S18 GUARD S3 VM IM S4 S5 1.25R DIFF R INTEGRATE 1k 2mA 10k 200 A 40pF C1 R1 R2 INT/IM SENSE AD53508 DAC1 DAC2 S6 S7 ENABLE SENSE S11 S12 S13 S14 S15 S16 S17 FORCE UNITY REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1999 AD53508-SPECIFICATIONS (T = 25 C, rated power supplies unless otherwise noted) A Parameter VOLTAGE FORCE/MEASURE MODE Voltage Swing, 2 mA Range 2 mA Drive 100 A Drive ACCURACY Gain ( 0.1% Tolerance) Offset Error Gain Nonlinearity (Relative to Endpoints) Current Measure CMRR (at MEAS_OUT) DRIFT Gain Error Temperature Coefficient Offset Drift CURRENT FORCE/MEASURE MODE RANGES 0 (High) 1 (Low) ACCURACY--HIGH RANGE Transconductance ( 3% Tolerance) Transresistance ( 3% Tolerance) Offset Error Gain Nonlinearity (Relative to Endpoints) Output Compliance Voltage-Induced Transconductance/Error DRIFT--HIGH RANGE Gain Error Temperature Coefficient Offset Drift ACCURACY--LOW RANGE Transconductance ( 3% Tolerance) Transresistance ( 3% Tolerance) Offset Error Gain Nonlinearity (Relative to Endpoints) Output Compliance Voltage-Induced Transconductance/Error DRIFT--LOW RANGE Gain Error Temperature Coefficient Offset Drift CURRENT MEASURE INTEGRATE MODE RANGES High Medium Low ACCURACY--HIGH RANGE Transresistance Error ( 3% Tolerance) Offset Error Gain Nonlinearity (Relative to Endpoints) Output Compliance Voltage-Induced Transresistance Error DRIFT--HIGH RANGE Gain Error Temperature Coefficient Offset Drift ACCURACY--MEDIUM RANGE Transresistance Error ( 3% Tolerance) Offset Error Gain Nonlinearity (Relative to Endpoints) Output Compliance Voltage-Induced Transresistance Error DRIFT-- MEDIUM RANGE Gain Error Temperature Coefficient Offset Drift Condition Min Typ Max Unit1 -4 -5 0.999 +9 +12 1.001 15 0.02 0.31 20 100 2.0 200 V V V/V mV % of Span mV/V ppm (PV or MV)/C V/C mA A Force Mode Measure Mode 0.776 1.21 0.8 1.25 0.824 1.29 40 0.05 +0.4 +10/-60 400 mA/V V/mA A % of Span A/V ppm (PV or MV)/C nA/C A/V V/mA A % of Span A/V ppm (PV or MV)/C nA/C A A nA Force Mode -0.2 Force Mode Measure Mode 77.6 12.1 80 12.5 82.4 12.9 4 0.05 +0.04 +10/-60 40 Force Mode -0.02 20.0 2.0 200 0.121 0.125 0.129 400 0.05 2.5 20 2 1.21 1.25 1.29 40 0.05 0.25 20 250 V/A nA % of Span nA/V of Output ppm MV/C nA/C V/A nA % of Span nA/V of Output ppm MV/C pA/C -2- REV. 0 AD53508 Parameter ACCURACY--LOW RANGE Transresistance Error ( 3% Tolerance) Offset Error Gain Nonlinearity (Relative to Endpoints) Output Compliance Voltage-Induced Transresistance Error DRIFT--LOW RANGE Gain Error Temperature Coefficient Offset Drift DISABLE MODE2 Voltage Swing, 2 mA Range 2 mA Drive 100 A Drive ACCURACY Gain ( 0.1% Tolerance) Offset Error Gain Nonlinearity (Relative to Endpoints) Current Measure CMRR (at MEAS_OUT) DRIFT Gain Error Temperature Coefficient Offset Drift OTHER SPECIFICATIONS Power Supply Rejection Ratio f < 40 Hz, VCC f < 40 Hz, VEE f = 40 kHz, VCC f = 40 kHz, VEE TAMB = +70C 70 60 35 25 1.2 0.02 CLOAD = 100 pF CLOAD = 2000 pF ZLOAD = 100 pF 50 k CLOAD = 20 pF Any Output Except Guards 8.5 2.5 -65 -25 20 2 50 2 20 10 0 1.0 2.4 0.8 10 14.0 -10.5 4.75 5 -15 15.0 -10.0 5.0 15.75 -9.0 5.25 15 -5 8 Condition Min 0.0121 Typ 0.0125 Max 0.0129 4 0.05 0.025 20 70 Unit1 V/nA nA % of Span nA/V of Output ppm MV/C pA/C -4 -5 0.999 +9 +12 1.001 15 0.02 0.31 20 100 V V V/V mV % of Span mV/V ppm (PV or MV)/C V/C dB dB dB dB nA % of Span s ms s s mA mA mV A V V A V V V mA mA mA CURRENT MEASURE HOLD MODE LEAKAGE CROSSTALK 3 SETTLING TIMES TO 0.01% Voltage Force and Guard Voltage Current Force (200 A Range) MEAS_OUT Pin SHORT CIRCUIT CURRENT LIMIT MAGNITUDE GUARD SCC LIMIT MAGNITUDE GUARD OFFSET (FROM SENSE INPUT PIN) IB (DAC1, DAC2) CURRENT DIGITAL INPUTS VIH VIL IIN (Input leakage current) POWER SUPPLIES VCC (Positive Analog Supply Voltage) VEE (Negative Analog Supply Voltage) VDD (Logic Supply Voltage) ICC (Positive Analog Supply Current) IEE (Negative Analog Supply Current) IDD (Logic Supply Current Is 0 with Inputs at Rails, Worst Case @ 2.4 V IN) NOTES 1 2 PV = Programmed Value, MV = Measured Value, FSR = Full-Scale Range = span. Output connected: DAC2 and 2 mA range selected, unconditionally. 3 f < 40 Hz, both channels in current force mode; other channel output voltage swinging rail to rail. Specifications subject to change without notice. REV. 0 -3- AD53508 ABSOLUTE MAXIMUM RATINGS* (TA = 25C unless otherwise noted) PIN FUNCTION DESCRIPTIONS Pin Name Description 2.5 V Reference Input First of Two Switchable Inputs Second of Two Switchable Inputs External RS and C Common External Capacitor External Resistor External Resistor Sense Input Force Output Guard Drive Output Measurement Output +15 V Analog Supply Connect Measure Output to Bus -10 V Analog Supply Force V (When Hi) or I (When Lo) Control Input Select DAC1 (When Lo) or DAC2 Control Input Control Input Select 2 mA Range (Active Lo) Select 200 A Range (Active Lo) Measure Forced Voltage or Current Connect Pin Drive (Active Lo) Connect Pin Drive (Active Lo) Select 200 A Range (Active Lo) Select 2 mA Range (Active Lo) Control Input Control Input Select DAC1 (When Lo) or DAC2 Control Input Force V (When Hi) or I (When Lo) Digital Ground Connect Measure Output to Bus +5 V Digital Supply Measurement Output Guard Drive Output Force Output Sense Input External Resistor External Resistor External Capacitor External RS and C Common Second of Two Switchable Inputs First of Two Switchable Inputs Unit V V V V mW C C C V Condition Min VDD to VEE VCC to VEE VDD to DGND Digital Inputs to DGND Power Dissipation Operating Temperature Range Storage Temperature Lead Temperature Force/Sense Outputs -0.3 -0.3 -0.3 -0.3 Max +26.4 +26.4 +6 VCC+0.3 700 TA +75C 70 +125 +300 VEE-0.8 VCC+0.8 25 -60 Soldering (10 sec) Or 75 mA, Whichever Is Less *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ORDERING GUIDE Model AD53508JP Temperature Range 25C to 70C Package Description Plastic Leaded Chip Carrier Package Option P-44A PIN CONFIGURATION C1 A EXT RC A DAC1 A EXT RC B C1 B 6 5 4 3 2 1 44 43 42 41 40 PIN 1 IDENTIFIER R2 A 7 SENSE A 8 FORCE A 9 GUARD A 10 MEAS OUT A 11 VCC 12 M CON A* 13 VEE 14 FORCE I A* 15 FORCE EN A* 16 DAC1 SEL A* 17 39 38 37 36 R2 B SENSE B FORCE B GUARD B MEAS OUT B AD53508 TOP VIEW (Not to Scale) 35 34 VDD 33 M CON B* 32 DIGGND 31 30 29 FORCE I B* FORCE EN B* DAC1 SEL B* 18 19 20 21 22 23 24 25 26 27 28 * = ACTIVE LO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 DSR_2.5 DAC2_A DAC1_A EXT_RC_A C1_A R1_A R2_A SENSE_A FORCE_A GUARD_A MEAS_OUT_A VCC M_CON_A* VEE FORCE_I_A* FORCE_EN_A* DAC1_SEL_A* INTEG_A* HOLD_A* I_RANGE0_A* I_RANGE1_A* VERIFY* OUTPUT_CON_A* OUTPUT_CON_B* I_RANGE1_B* I_RANGE0_B* HOLD_B* INTEG_B* DAC1_SEL_B* FORCE_EN_B* FORCE_I_B* DIGGND M_CON_B* VDD MEAS_OUT_B GUARD_B FORCE_B SENSE_B R2_B R1_B C1_B EXT_RC_B DAC1_B DAC2_B DAC2 A DSR 2.5 DAC2 B DAC1 B R1 A VERIFY* OUTPUT CON A* INTEG A* HOLD A* I RANGE0 A* OUTPUT CON B* I RANGE1 B* I RANGE1 A* I RANGE0 B* HOLD B* INTEG B* R1 B * = Active Lo CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD53508 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE -4- REV. 0 AD53508 Table I. Data Table Data Latch Bits S1 S2 S3 S4 S5 S6 S7 S9 S17 S8 S13, S10 S15, S14 S16 S11 S12 S18 Voltage Force/Current Measure Irange 0 On Off On On Irange 1 On Off On On Integrate Range On Off On On Integrate On Off On On Hold/Measure On Off On On Current Force/Voltage Measure Irange 0 On On Off Off Irange 1 On On Off Off Disable Mode: Output Connected X X X On Verify/Voltage Force On On Off Verify/Current Force On Off On Disconnect X X X On Off On X Off Off Off Off Off On On On On On Off Off Off Off Off Off Off Off Off On Off Off Off Off On On On On On Off On On On Off Off On Off Off Off Off Off On Off Off Off Off Off On On Off Off Off On On On On On On On On On On Off Off On Off X On On Off On On X Off Off Off On Off Off X On Off Off Off Off Off On X Off Off Off Off Off Off X On On On On On Off X On On X On On On X On Off On On On Off X Off On Off Off Off Off X Off Off Off Off Off Off X Off Off Off Off Off On X On On On On On Off X DAC2 Select: Enabled X X X CAPACITOR CHARGE INTEGRATE* INTEGRATE HOLD* * = ACTIVE LO DISCHARGE CAPACITOR HOLD Figure 1. Integrate/Current Measure Timing Diagram Table II. Truth Table * = Active LO Control Input M_CON* VERIFY* FORCE_I* FORCE_EN* DAC1_SEL* INTEG* HOLD* I_RANGE0* I_RANGE1* OUTPUT_CON* DAC1 LO HI HI LO LO HI HI LO HI LO DAC2 LO HI HI LO HI HI HI LO HI LO DAC1 LO HI HI LO LO HI HI HI LO LO DAC2 LO HI HI LO HI HI HI HI LO LO FV/MI 2 mA FV/MI 200 mA FV/MI Integrate DAC1 Voltage Settle LO HI HI LO LO HI HI HI HI LO Integrate LO HI HI LO LO LO HI HI HI LO Hold LO HI HI LO LO LO LO HI HI LO FV/MI Integrate DAC 2 Voltage Settle LO HI HI LO HI HI HI HI HI LO Integrate LO HI HI LO HI LO HI HI HI LO Hold LO HI HI LO HI LO LO HI HI LO DAC1 LO HI LO LO LO HI HI LO HI LO DAC2 LO HI LO LO HI HI HI LO HI LO DAC1 LO HI LO LO LO HI HI HI LO LO DAC2 LO HI LO LO HI HI HI HI LO LO DAC1 LO LO HI LO LO HI HI X X LO DAC2 LO LO HI LO HI HI HI X X LO DAC1 LO LO LO LO LO HI HI X X LO DAC2 LO LO LO LO HI HI HI X X LO X X X X X X X X X HI FI/MV 2 mA FI/MV 200 A FV/Verify FI/Verify Disconnect Disable Output Connected X X X HI X X X X X LO REV. 0 -5- AD53508 PPMU APPLICATION NOTES The PPMU can be used in two modes: 1. VOLTAGE FORCE with CURRENT MEASURE or VERIFY CURRENT FORCE; 2. CURRENT FORCE with VOLTAGE MEASURE or VERIFY VOLTAGE FORCE. In both modes the following setup is recommended: 1. The value of the external integrate capacitor (EXT_RC to C1) is 10 nF. 2. MEAS_OUT pin is loaded with 1 M to ground. 3. VCC = +15.0 V, VDD = +4.5 V, DIGGND = 0.0 V, VEE = -10 V, DSR = 2.5 V unless otherwise stated. 4. A 10 resistor in series with the FORCE pin. 5. A 1 k resistor in series with the SENSE pin. IN VOLTAGE FORCE WITH CURRENT MEASURE OR VERIFY CURRENT FORCE 4. Computations for F1 are: F1 x 0.25 = LOW + 1 x (HIGH - LOW)/4 F1 x 0.50 = LOW + 2 x (HIGH - LOW)/4 F1 x 0.75 = LOW + 3 x (HIGH - LOW)/4 Where LOW = -Full Scale and HIGH = +Full Scale. The linearity tests for measuring current are as follows (at the MEAS_OUT pin): 1. The voltage is constant for these measurements. 2. The four ranges (M1, M2, M3, M4) correspond to CURRENT MEASURE ranges (200 nA, 20 A, 200 A, and 2 mA respectively). 3. The endpoints of the linearity curve are determined by the -full scale (or LOW), and the +full scale (or HIGH) readings at the same FORCE pin voltage. 4. Using these endpoints, gain nonlinearity is computed and tested at the 1/4 scale, 1/2 scale, and 3/4 scale points. 5. Computations for M1 are: M1 x 0.25 = LOW + 1 x (HIGH - LOW)/4 M1 x 0.50 = LOW + 2 x (HIGH - LOW)/4 M1 x 0.75 = LOW + 3 x (HIGH - LOW)/4 Where LOW = -Full Scale, and HIGH = +Full Scale. The M_CON pin can be used for disconnecting the MEAS_OUT pin by: 1. Raising M_CON to 2.4 V. 2. Measuring MEAS_OUT (which is loaded with 100 k). 3. MEAS_OUT should ideally be 0 V. The OUTPUT_CON pin can be used for disconnecting the DUT by: 1. Disabling the SENSE pin (OUTPUT_CON = 2.4 V). 2. Loading FORCE_OUT with 2 k to ground. 3. Programming the DAC1 input to +FS (+9 V) and measuring the FORCE_OUT voltage (FV1). 4. Programming the DAC1 input to -FS (-4 V) and measuring the FORCE_OUT voltage (FV2). 5. FV1-FV2 < 1.3 mV. 6. A change of 1.3 mV implies a switch off-resistance of 20 M. S8 S9 SENSE 1k To measure the leakage in the current measure and hold mode, the PPMU has to be into the Force Voltage/Measure Current Integrate mode. 1. The FORCE_A (Force Output) pin has to be programmed to +9 V. 2. The PPMU has to be programmed to INTEGRATE mode. 3. The PPMU has to be programmed to HOLD mode. 4. Sample MEAS_OUT. 5. Wait 100 ms. 6. Sample MEAS_OUT again. 7. The difference between 2 and 4 must be less than 15 mV. The linearity tests for forcing voltage are as follows (at the FORCE pin): 1. The four ranges of CURRENT MEASURE ranges (200 nA, 20 A, 200 A, and 2 mA) correspond to F1, F2, F3, and F4. 2. The endpoints of the linearity curve are determined by -full scale (or LOW), and the +full scale (or HIGH) readings at the same FORCE pin current. 3. Using these endpoints, gain nonlinearity is computed and tested at the 1/4 scale, 1/2 scale, and 3/4 scale points. AD53508 FORCING VOLTAGE DAC1 DAC2 S6 S7 ENABLE SENSE EXT RC MAIN S10 VF IF S4 S5 1.25R INTEGRATE 1k 2mA R 10k 200 A 40pF C1 R1 R2 INT/IM S11 S12 S13 S14 S15 S16 S17 FORCE 10 TO DUT DSR 2.5V S2 OUTPUT S1 S3 VM IM DIFF UNITY MEAS OUT CON 1.25R R GUARD S18 GUARD Figure 2. Guarded Voltage Force/Current Measure, IRANGE 1: I 2 mA -6- REV. 0 AD53508 IN CURRENT FORCE WITH VOLTAGE MEASURE OR VERIFY CURRENT FORCE 7. Measure voltage at MEAS_OUT and compare to 4. 8. VCC = 15 V. 9. DAC1 = 0 V. 10. FORCE pin loaded with -4 V source. 11. Measure current at FORCE. 12. Measure voltage at MEAS_OUT. 13. VEE = -9.5 V. 14. Measure current at FORCE and compare to 11. 15. Measure voltage at MEAS_OUT and compare to 12. 16. VEE = -10 V. VOLTAGE FORCE WITH CURRENT MEASURE (2 mA RANGE) The linearity tests for forcing current at the FORCE pin: 1. The FORCE pin is loaded with a voltage source. 2. The two ranges of CURRENT FORCE ranges (2 mA and 200 A) correspond to F1 and F2. The endpoints of the linearity curve are determined by full scale (or LOW), and the full scale (or HIGH) readings at the same FORCE pin voltage. 3. Using these endpoints, gain nonlinearity is computed and tested at the 1/4 scale, 1/2 scale, and 3/4 scale points. 4. Computations for F1 are: F1 x 0.25 = LOW + 1 x (HIGH - LOW)/4 F1 x 0.50 = LOW + 2 x (HIGH - LOW)/4 F1 x 0.75 = LOW + 3 x (HIGH - LOW)/4 Where LOW = -Full Scale and HIGH = +Full Scale. The linearity test for measuring voltage is as follows (at the MEAS_OUT pin): 1. The endpoints of the linearity curve are determined by the -full scale (or LOW), and the +full scale (or HIGH) readings. 2. Using these endpoints, gain nonlinearity is computed and tested at the 1/4 scale, 1/2 scale, and 3/4 scale points. 3. Computations for M1 are: M1 x 0.25 = LOW + 1 x (HIGH - LOW)/4 M1 x 0.50 = LOW + 2 x (HIGH - LOW)/4 M1 x 0.75 = LOW + 3 x (HIGH - LOW)/4 Where LOW = -Full Scale, and HIGH = +Full Scale. CURRENT FORCE WITH VOLTAGE MEASURE (2 mA RANGE) 1. DAC1 = 9 V. 2. FORCE pin loaded with 2 mA current source. 3. Measure voltage at FORCE. 4. Measure current at MEAS_OUT. 5. VCC = 14.25 V. 6. Measure voltage at FORCE and compare to 3: Limit = 237 V. 7. Measure current at MEAS_OUT and compare to 4: Limit = 237 V. 8. VCC = 15 V. 9. DAC1 = -4 V. 10. FORCE pin loaded with 2 mA current sink. 11. Measure voltage at FORCE. 12. Measure current at MEAS_OUT. 13. VEE = -9.5 V. 14. Measure voltage at FORCE and compare to 11: Limit = 474 V. 15. Measure current at MEAS_OUT and compare to 12. 16. VEE = -10 V. 1. DAC1 = 5 V. 2. FORCE pin loaded with 9 V source. 3. Measure current at FORCE. 4. Measure voltage at MEAS_OUT. 5. VCC = 15 V. 6. Measure current at FORCE and compare to 3. AD53508 FORCING VOLTAGE DAC1 DAC2 S6 S7 ENABLE SENSE EXT RC MAIN S10 VF IF S4 S5 1.25R INTEGRATE 1k 2mA R 10k 200 A 40pF S8 S9 SENSE C1 R1 R2 INT/IM S11 S12 S13 S14 S15 S16 S17 FORCE DSR 2.5V S2 OUTPUT S1 S3 VM IM DIFF UNITY MEAS OUT CON 1.25R R GUARD S18 GUARD Figure 3. Guarded Current Force/Voltage Measure, IRANGE 1: I 2 mA REV. 0 -7- AD53508 1 51 52 34 39 40 41 32 VCC VH 47 VTERM 45 DATA 37 DATA 38 IOD 43 IOD 42 RLD 49 RLD 50 VL 31 HCOMP 16 LEH 13 LEH 12 QH 7 QHB 6 COMPARATOR QL 4 QL 3 VEE 39nF CHDCPL 39nF CLDCPL TO DUT TO DUT (SENSE) GUARD AD53032 C3609-2.5-10/99 PRINTED IN U.S.A. 25 VHDCPL VOUT VLDCPL 50 DRIVER 30 22 LEL 11 LEL 10 LCOMP 17 VCOMI 25 IOLC 30 IOLRTN 22 IOHRTN 27 INHL 36 INHL 35 1.0 A/K IOHC 29 V/I 9, 33, 44, 46, 48 2, 5, 8 19 28 14 26 15 "CONNECT TO HIGH QUALITY, LOW NOISE SIGNAL (GND)" ACTIVE LOAD +1 V/I 24 23 VCOMS DSR IOL FORCE * PPMU IOH THERM DAC1 NC DAC2 MEAS_OUT GUARD* SENSE PWRGND ECLGND HQGND2 HQGND TO V/I DAC (PER CHANNEL) TO SYSTEM VOLTMETER FROM OTHER PMUs Figure 4. Recommended Use of the PPMU with a DCL OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 44-Lead Plastic Leaded Chip Carrier (PLCC) (P-44A) 0.180 (4.57) 0.165 (4.19) 0.048 (1.21) 0.042 (1.07) 0.048 (1.21) 0.042 (1.07) 6 7 PIN 1 IDENTIFIER 0.056 (1.42) 0.042 (1.07) 40 39 0.025 (0.63) 0.015 (0.38) 0.050 (1.27) 0.63 (16.00) BSC 0.59 (14.99) 0.021 (0.53) 0.013 (0.33) 0.032 (0.81) 0.026 (0.66) 0.040 (1.01) 0.025 (0.64) 0.110 (2.79) 0.085 (2.16) TOP VIEW (PINS DOWN) 17 18 29 28 0.020 (0.50) R 0.656 (16.66) SQ 0.650 (16.51) 0.695 (17.65) SQ 0.685 (17.40) -8- REV. 0 |
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